Fun with Xilinx

I just spent pretty much the whole day getting a Spartan 3E to load from an SPI PROM.

Turned out to be this problem.  Apparently, if the trace on CCLK gets too long, or is otherwise strange, the internal logic can get confused and send 0x10 to the PROM as a read command instead of 0x0B.

I ended up cutting off part of the trace (which will have to be reinstated eventually, so the processor can write to the PROM for updates, unless I decide to route that through the FPGA after loading the initial image via JTAG) and terminating the now-far end (at the PROM) with 330Ω resistors to +3.3V and GND, so effectively about 165Ω to half-supply.

Then I had yet more fun with iMPACT.  I'm building the .bit file on my Linux workstation, then configuring the board with the Windows machine in the lab; the actual files live on the BSD box.  Apparently this confuses iMPACT, and regenerating a previously-generated .mcs file, for PROM programming, will just use the old data rather than reading the new .bit file.  Wunnerful.

Well, my XC3S500E is now loading in about 120 ms using CCLK25, so I guess I'm happyish.  Now I need to tweak some of my logic to get rid of a timing error that cropped up when a MUX got too big....