In anticipation of one or more projects involving small-to-medium FPGAs, I'm setting out to learn more about the options.
I'd done some playing around with the Xilinx parts in the space of interest (Spartan 3E). They look fairly promising. The competition comes down to Altera (Cyclone II), and, now that I take a closer look, Actel (ProASIC3 / Igloo).
I have the Altera software installed on my office Windows box, but haven't done much with it. For the application at hand, as it turns out, Altera is pretty much disqualified on grounds of not offering the right amount of logic in a small enough package without resorting to insanely fine-pitch design rules (there's about enough space for a 100-lead VQFP, but, for Altera, 144 leads seems to be the minimum). [Update: The junior member of the plain-vanilla Cyclone family is available in a 100-lead TQFP; while it lacks some of the nifty features of Cyclone II/III and Spartan 3E, it seems quite adequate for the current task - which puts Altera back in the running.] Given that I only need three inputs and one output for the application (plus five pins for the supervisory interface), even a 100-pin part is overkill in the I/O department.
I hadn't really been thinking of Actel, partly because I was remembering them from the mid-90s (antifuse FPGAs and a really expensive development environment) and partly because, the last time I'd looked at their newfangled flash-based parts, the development software was still out of my price range, unless I had a solid (and funded) requirement.
Well, now the development software is a free download, though it's even more obnoxiously encumbered than Altera's (node- and date-locked, requiring a new free license every year, in addition to the free version being Windows-only), and there's a cheap eval kit for the Igloo (the kit's called an Icicle, and Mouser has them for $108.something), so I got myself one of the kits, downloaded the software, and went through all the weirdness of getting a license.
(Setting up FlexLM manually is a nuisance. Apart from anything else, the Windows environment-variable editor, like sundry other things in the Windows world, deals with potentially long lists of potentially long strings in a little bitty, non-resizeable window. Talk about sucky UI design!)
Anyway: my first impression of Libero is that it'll get the job done, eventually, but that it's nowhere near as well designed as Xilinx's ISE. It appears that each stage of the build process is meant to be invoked manually (no "make" button), and I'm not finding a nice summary of resources available vs. resources used (which is right there on the front page of an ISE project).
Determining resource usage is going to be important in evaluating parts for a given application... maybe I'll find the information I need, hidden somewhere, when I get around to wading through the manual.
The time-locked license may be an issue for the client, too; the prospective product is meant to have a 20-year support cycle, and having the ability to maintain a stable development environment is important. This may yet push the whole thing back to the Xilinx platform.
Apart from the development-software issues, the ProASIC3 does have a certain amount of promise for the application at hand: it seems to be available from stock in the right combination of size, package, and temperature range, at a decently low price; the instant-on characteristic is a good thing; and the 1K bits of user flash could prove useful for storing model-specific parameters, leaving the actual Verilog program invariant (I'd been planning to use an external serial memory for that purpose, but the ProASIC3 could be a one-chip solution).
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