...two-input, open-collector (or open-drain), OR gates. Like, two of them. In the cute little SOT-23-5 packages, please?
Alas, the open-collector OR gate appears to be a mythical beast. So, I'm stuck with using NORs and transistors.
(The project at hand is a USB-to-async-serial bridge with some special properties. Like, the async serial side is 3.3V logic level, and RTS and DTR are gated, net-non-invertedly, to pins that control LPC2xxx in-system programming. The logic is: if the RTS or DTR pin of the bridge chip is low, and the enable is active (for sufficiently arbitrary values of active), then the corresponding connector pin needs to be pulled low. Actually, a DPST switch would do the trick, but would occupy too much board space.)
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