I mentioned as how the ARM SSP (synchronous serial port, for SPI and suchlike) lacks an "operation entirely complete" interrupt?
Turns out that, as an SPI slave (at least as observed in the NXP LPC13xx), it insists on having SSEL deasserted after each and every frame (byte).
This is severely annoying.
I'd observed long ago that SSEL in master mode was per frame, not per block, so the AGROS driver, by default, simply ignores the availability of SSEL and uses a GPIO pin as a per-block select, as required by most SPI peripherals, such as chained drivers, SPI memory devices, and so on.
The corresponding limitation in slave mode is seriously crippling, if one is trying to work with a master that uses SSEL to define a block transfer. (The Aardvark does this. I'm still waiting for the detailed specs on the gadget I need to work with.)
Oh, and the ARM implementation doesn't work in a daisy-chained setting either, so that's no justification. Set the frame length to 8 bits, bring SSEL low, clock in 48 bits, and what comes out of the FIFO is the first 8 bits, not the last. (Besides, were it daisy-chained, the next device in the chain would be getting the data loaded into the transmit FIFO, rather than the excess bits from the SPI frame.)
And yet, somehow, this cell has become The Standard for use in ARM-based MCUs.
- This malfeature is indeed baked into ARM PrimeCell PL022.
- Turns out ST doesn't use PL022; the STM32's SPI cell looks like it handles SSEL the way it's normally done in the real world.
- So, maybe I use an STM32 eval board for this gadget, instead of the LPC1xxx eval board. (Or I could probably use an AVR, whose SPI looks to be simple and well-behaved.)
- But - and this is the fun part - I think the other side of the interface is an STM32, which may make life interesting, given that the side I'm trying to emulate is apparently built around an LPC, and their SPI implementations are incompatible.
Oh, well... the abovementioned fun part is Somebody Else's Fun, and a workaround is possible, albeit kludgey.