I did actually have a productive day (or at least it seems so, pending confirmation of a timing spec).
Got a small but critical subsystem of the new FPGA logic working.
Using a 300 MHz clock. In a relatively cheap FPGA (not quite the low end of the Spartan 6 range).
Based on my understanding of how the end product is used, this implementation ought to be fine. If not... well, then we're looking at adding old-timey delay lines to make the whole mess asynchronous, and keep the timing totally consistent relative to the input signal, instead of having ±1.67ns timing uncertainty.
And, assuming this part is OK, the rest is easy. Significantly more complex in terms of gates and functionality, but straightforward.