I've been known to kvetch, from time to time, about the proliferation of 8250-descended UARTs, and how their lack of a "transmit complete" interrupt makes life difficult for those of us who sometimes have to deal with an old concept called "half duplex" (y'know, like some old-timey modems, or modern 2-wire RS-485).
Well, the ARM SSP (Synchronous Serial Port), as used by NXP, has a similar lack: while the status register has a "transmit FIFO empty" bit, it's not brought over to the interrupt status register... so there's no way to get an interrupt when the last of the data you'd loaded into the TX FIFO has been sent (or, at least, loaded into the shift register) and it's time to rescind the "data available" signal you're sending to the SPI master.
And, even when you are the master, it's highly convenient to have an interrupt for "the last byte you loaded into the TX FIFO has now been clocked out of the shift register, and the TX path is bare." For, y'know, controlling SSEL outputs when you might have several or the built-in SSEL just doesn't do the right thing. (In the AGROS driver, I ended up using the receive-timeout interrupt for end-of-transmission, though that's delayed by some unspecified "timeout period.")
So, another pollish driver. Fortunately, the application at hand is a tiny standalone thing.
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