Let's see... I've had issues with reverse current (and its change with temperature) a few times. Forward voltage, once in a while. The diode property of the day is...
Perfectly straightforward circuit. Gate of FET has a weak pulldown to handle startup conditions. Logic can drive gate HIGH or LOW via a 10K resistor (a value that can't be much reduced due to constraints elsewhere in the circuit). A pair of global enable signals, when in the LOW-to-disable state, pull the gate LOW through Schottky diodes of a familiar type. So, the global enables and the logic all have to agree that the FET should be turned on before it gets voltage (in excess of a Schottky drop @ low current) applied to the gate.
All seemed well, until, in checking out a reported timing issue on the tens-of-milliseconds scale, I observed that there was a microsecond-scale ACTIVE pulse on the output of the FET when the enables went HIGH, but before the logic had gotten around to taking action.
Oog. Edge getting coupled backward through the diodes? Edge getting coupled backward through the diodes. Capacitively. Turns out those suckers have 60 pF typical junction capacitance, each.
Tossing in a 470 pF cap from gate to ground suppresses the pulse, without obvious untoward effects.
A possibly better solution is to swap the diodes for a footprint-compatible model of adequate specs for the application and 2 pF maximum junction capacitance @ 0V.