Spent a few hours bashing my head against a weird bug in a new feature I'd just added to the FPGA logic for Project Egbert. (Would've been less time, but there's compilation delay, then download delay, and it makes for slow testing.)
It was a definite Heisenbug. With Firesign Bilocation (i.e., it was in two places at once when it wasn't anywhere at all).
I could make it come and go by adding or removing certain lines of Verilog code. In a synchronous section. Dependent entirely on synchronous signals.
And, when it manifested itself, it didn't just misguidedly assert the status bit the new code was meant to affect. Oh, no. It also goofed up some other, unrelated logic. Oh, and it manifested itself at impossible times, when the necessary trigger condition wasn't present.
This morning, in among surfing the Net and before going back to bed, I decided to route the internal state of the buggy feature to a register I could read back, just to see what was going on. Naturally, this made it start working.
So I removed the debug route. Now it works.
I'm developing a great mistrust toward Verilog for Xilinx. But maybe a newer version of ISE would fix the problem. And, maybe, introduce new ones. (Update from 11.1 to 11.5? But the updater says my license doesn't cover some features of the new version. And doesn't tell which those might be. Hmph. Ah, but if I tell it to go ahead, and it tells me the license is OK for everything except DSP tools, which I don't know how to use anyway. And 12.1 is scheduled for release month-after-next. Treadmill!)